This disclosure relates to integrated circuit devices, and more specifically, to a method and structure to reduce capacitance between gate and source/drain contact structures in semiconductor devices.
As the dimensions of modern integrated circuitry in semiconductor chips continue to shrink, conventional semiconductor processing is increasingly challenged to make structures at finer dimensions. Not only is the circuit density increasing, but the performance of the devices needs to remain high. The goals of high performance and high density conflict when the higher density causes undesired interactions between circuit elements. For example, as contact stubs and trenches come closer and closer to the gate structure, parasitic capacitance and gate to source/drain coupling are increased, thus degrading performance.